Memory cells of conventional semiconductor devices have a dielectric capacitor, for example. The dielectric capacitor includes a bottom electrode, a dielectric layer and a top electrode stacked on one another in this order.
Typically, such semiconductor devices are formed by sequentially forming the top electrode, the ferroelectric layer and the bottom electrode by patterning using different masks. In this process, for example, an array of a plurality of top electrodes arranged in columns and rows is formed by patterning, and then, a dielectric layer is patterned by using a mask that integrally covers a plurality of top electrodes arranged in a column or row and a peripheral region thereof. Similarly, the bottom electrode is formed by patterning using a mask that integrally covers the column or row of top electrodes, the dielectric layer and the peripheral region thereof.
In general, etching of a layer of a material, such as a conductor and a dielectric, depends on the density of the pattern.
For example, in the case where capacitors 50 are arranged in a matrix as depicted in FIGS. 9A and 9B, a top electrode 23, a dielectric layer 22a, a bottom electrode layer 21a or the like is etched in sparse regions (upper and right regions in FIG. 9A) or adjacent regions. When the dielectric layer is etched in the sparse regions, a reaction product 56 is likely to be deposited on the side wall of a mask 55 as depicted in FIG. 9B. After the mask 55 is removed, the deposited reaction product 56 remains in the form of a fence-like residue.
The fence-like residue causes degradation of coverage of a protective film formed on the capacitors. In addition, the fence-like residue causes leakage between capacitors and thus deteriorates the characteristics of the semiconductor device.
To solve the problem, in Japanese Patent Laid-Open No. 2000-150809, there is described a method that does not suffer from the effect of a fence-like residue of a reaction product that occurs in etching of a dielectric layer by adapting the shape of a bottom electrode and a dielectric layer.
In addition, in Japanese Laid-Open Patent Publication No. 2003-152108, there is described a method that overetches a conductive layer or dielectric layer using a mask whose upper surface is rounded, thereby preventing adhesion of a reaction product having a low vapor pressure to the side wall of the mask.
In addition, in Japanese Laid-Open Patent Publication No. 2001-244432, there is described a method that removes a reaction product adhering to the side wall of a mask by cleaning the side wall with phosphoric acid after etching.